The present invention relates to a circuit and method for reducing stress on an output device. More specifically, the present invention relates to an HCI stress circuit and method using low voltage devices adapted to limit voltage across an output device, thereby reducing HCI stress.
In modern CMOS ASIC designs, the core circuitry generally operates at a lower voltage than the IO circuits. This provides a core circuitry design that operates at higher speeds with lower power consumption. However, since the maximum operating voltage of such current CMOS ASIC core circuitry designs is also lower, these devices may not be used directly with currently known IO circuits without special design considerations. In particular, stress on the IO circuits must be taken into consideration when designing CMOS ASIC circuits.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.